1. Field of the Invention
The present invention relates to an apparatus and a computer implemented method for circuit design verification and a computer product program for controlling a computer system so as to verify circuit designs and in particular to a functional simulation technology of a large scale integrated circuit (LSI) so as to obtain invaluable analysis results of RTL coverage.
2. Description of the Related Art
Along with rapid progress in larger scales and complexity of circuits such as LSIs in recent years, there is a growing movement to divert previously created design assets at designing the stage for new circuits. When designing a circuit by diverting the design assets, information on verification quality of a diverted circuit design is very important. For the information on verification quality, register transfer level (RTL) code coverage information and functional coverage information are, in general, widely used. The “RTL code coverage information” is information about which description is executed out of an entire circuit descriptions stated in the RTL when functional simulation is executed. A designer can recognize how many circuit descriptions executed in the functional simulation by a numerical value, such as a percentage, by referring to the RTL code coverage information and thereby obtain an indication for measuring the verification quality. The RTL code coverage includes state coverage, branch coverage, and toggle coverage as described later. In addition, the RTL code coverage may sometimes include condition coverage, state coverage and arc coverage. The condition coverage highlights problems with control variable values, control logic operators and helps to identify untested or redundant branching operations. The state coverage identifies untested or dead states and the arc coverage indicates the degree of execution of possible transitions among states in FSMs (Finite State Machines).
In conventional design verification systems used for analyzing the RTL code coverage, there has been some attempt to improve the analysis. For example, detailed results for individual functional blocks inside the circuit are displayed in graphs, the identifiers of the functional blocks are displayed in order of low-coverage, and the functional blocks that fail to complete requirements are displayed in a color, such as red. However, in any case, the conventional design verification systems are generally configured to directly display calculation results obtained by the functional simulation.
With reference now to FIG. 1, an example of the contents of a display in the conventional design verification system is illustrated. FIG. 1 represents results of verifying the degree of achievement in the RTL code coverage of the LSI and functional blocks inside the LSI expressed in the register transfer level (RTL) descriptions by executing the functional simulation with test patterns or verification patterns. As shown in FIG. 1, a column of “state coverage” for indicating a rate of execution of respective statements or rows in the executable RTL descriptions, a column of “branch coverage” for indicating a rate of execution of true and false responses concerning executable branch sentences, and a column of “toggle coverage” for indicating a rate of 1 and 0 values applied by connection wiring of the RTL descriptions are displayed. A row “total” for indicating results of an entire module (the functional blocks inside the target LSI), and a row “Abcd” for indicating results of some sub-modules constituting the entire module are also displayed. The value (95.7%) in the upper part of the “total” and the “state coverage” section in FIG. 1 indicates a value of the state coverage of the target LSI. The value of the denominator (1286) in the fraction indicates the total number of statements in the RTL descriptions for the functional blocks of the target LSI, the value of the numerator (1231) indicates the number of statements activated by the test pattern, and the value in parenthesis (55) indicates the number of statement not activated by the test pattern.
As shown in the example of FIG. 1, when the design verification is executed with a newly developed LSI, it is usually rare for the state coverage, the branch coverage or the like to reach 100% in the first simulation. Therefore, the designer has to verify the non-active portions one-by-one, and execute the functional simulation again by adding new test patterns when the verification is insufficient. Such additional verifications are executed until predetermined standards are satisfies, then the results of the verification are registered with the design verification system for use in confirmation of the verification or for reference by a third party.
However, in reality, there are many cases where the predetermined coverage standards are not achieved by the repeated simulation with new test patterns. The main reasons areas follows. First, a mixture of redundant RTL descriptions is present. For example, a mixture of specific redundant descriptions attributable to a request from a logic synthesis tool or redundant descriptions attributable to specifications of the logic synthesis tool is present. Second, redundant RTL descriptions due to reasons specific to a product under development are present. For example, redundant descriptions in anticipation of future necessities, adoption of redundant descriptions in light of future expansions that are not used in the production under development are present, or there are reuses of some functional blocks from another product including descriptions concerning functions which are not used in the product under development. Further, there are occasional provisions of redundant flip-flops (flip-flops which are only set to 0 and 1) by an RTL designer for easy reading of the RTL descriptions.
Of course, there is also a case where the quality of the produced functional verification pattern is insufficient and some RTL code that is supposed to be activated or verified remains non-active, which is especially typical in the product under development. Therefore, to obtain precise information of the RTL code coverage for the product under development, “redundant non-active or unverified portion” (hereinafter called “the redundant non-active portion”) which does not affect the product under development should be excluded by analyzing the result of the functional simulation for the circuit. Therefore, there has been a large problem that the invaluable verification result could not be obtained by only registering and displaying the results obtained by the functional simulation directly.